The present application has been filed concurrently with, and is related to, U.S. patent applications, Ser. Nos. 555,027, filed Nov. 25, 1983 (now U.S. Pat. No. 4,570,220) and 555,026, filed Nov. 25, 1983 (abandoned in favor of continuation in part application, Ser. No. 823,358, filed Jan. 28, 1986), and hereby refers to, and incorporates by reference the contents of the above referenced applications.
1. Field of the Invention:
The present invention relates to apparatus and methods for transferring data between a source and a plurality of receiving data processing devices. More particularly, the present invention relates to data transfer along a bus between a source and a plurality of data processing and peripheral devices using multiple bus structures.
2. Art Background:
In the computing industry it is quite common to transfer data and commands between a plurality of data processing devices, such as for example, computers, printers, memories, and the like, on a system or data bus. A data processing system typically includes a processor which executes instructions that are stored at addresses in a memory. The data that is processed is transferred into and out of the system by way of input/output (I/O) devices, onto a bus which interconnects the data processing system with other digital hardware. Common constraints on the speed of data transfer between data processing devices coupled to a bus are protocol or "handshake" restrictions which require a predetermined sequence of events to occur within specified time periods prior to actual data exchange between the devices.
Various methods have been devised in order to convey data between a data processing device and a peripheral unit which may be, for example, a memory unit, a second processor unit, a disk drive or the like. One method utilizes direct memory transfers which permits large quantities of information to be moved between a processor memory and a peripheral unit. However, one disadvantage of existing direct memory transfer system is that some processor activity is necessary for each direct memory transfer. Various instructions or other signals are required which start and stop the transfer, and the generation of these signals requires an interruption of the processor unit. In data processing systems which utilize multiple processors, a direct memory transfer between the memory of a first processor and the memory of a second processor requires complex system protocol and addressing in order to preclude ambiguity. For example, the transfer of data between a local resource memory of a primary processor A and the local resource memory of a secondary processor B along a common bus typically requires the interruption of secondary processor functions in order to access the secondary memory and initiate a data transfer along the bus to the primary processor. In addition, any overlapping of memory addresses between the primary processor's memory and secondary processor's memory further complicates the data transfer protocol in order to insure no ambiguity with respect to the contents of each memory at identically numbered address locations. Accordingly, in multiple processor data processing systems, it is apparent that proper allocation and access of system resources is vital in order to insure optimum efficiency in data transfers.
As will be described, the present invention provides a data processing system architecture which includes multiple bus structures in order to optimize data and message transfer between multiple processors, as well as an orderly allocation of system resources to all devices residing within each bus. The present invention's bus structure comprises a general purpose parallel bus, as well as specialized buses which are interconnected through system interfaces which define the communication and data transfer protocols.